In multiprocessor computer systems employing synchronous clocking schemes, it is generally necessary to distribute many copies of a low skew clock signal over long distances. Clock skew is regarded as a principal design parameter with regard to the design and implementation of high-speed, distributed clock systems. Clock skew is generally understood in the art as a difference in time between the rising edge of one clock pin relative to another clock pin. Clock skew is generated by differences in delay between the system clock oscillator and the clock pins. This delay typically results from a combination of the delay through different clock drivers and the time required for the clock signals to propagate down the PC board trace wires, often referred to as trace delay.
The clock driver chips employed in large digital systems are typically limited in terms of the number of driver outputs, thus requiring that several chips be connected in a parallel clock signal repowering configuration. It is possible, through careful designing, to minimize driver-to-driver skew on a single chip using various layout and circuit design techniques, such as optimizing wiring and device matching.
Clock driver skew with respect to a chip-to-chip configuration, however, is primarily a function of chip process variations, and generally can not be controlled adequately through good physical and circuit design practices. Further complicating the effort of designing multiple-chip clock distribution circuitry is card-to-card skew. Such card-to-card skew may be due to either process variations or technology variations.
A known approach to addressing chip-to-chip and card-to-card clock skew involves the use of one or more phase lock loop (PLL) circuits per chip. PLL's are typically employed in prior art designs to provide a requisite level of clock signal phase alignment. The use of PLL's in accordance with prior art approaches, however, generally complicates the clock distribution scheme, since PLL's typically require unique wiring blockage, layout, power distribution, and characterization. Additionally, crosstalk becomes a concern when using more than one PLL per chip.
There exists a keenly felt need for a clock distribution architecture that overcomes the above-noted deficiencies found in prior art implementations, and one that provides for low clock skew in chip-to-chip and card-to-card configurations. The present invention fulfills these and other needs.